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Information / general / Using gf180mcu_ocd_io in LibreLane
After 04/30/2026 23:59
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Seems to happen in io_inv_2i inside the input path.
16:38
There is a pmos whose source is wired to VDD (core) and nwell is biased by DVDD.
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As for 5V operation, doing some quick tests now. Seems all fine. I'm feeding 3.0V as Vcore and 5.0V as Vio and works just fine AFAICT.
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There isn't any big change in performance. The measure rise time is longer but it's a bit of an artefact of the output shape.
09:04
09:05
There is a bit of a slow down right before hitting 80% and so that makes the measure point be almost twice as long ... I'd need to check if that's also in simulation. Could be non-linear capacitance/load on the line from the RP2350 chip being on that line.
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@Tim Edwards ^^
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Tim Edwards 05/04/2026 23:48
Or it could be from the latching stage of the level shifter.
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@Tim Edwards There is the same effect in the GF provided default IOs when powered at 3.3V so I don't think it's related to anything you did.
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I think it's an artefact of the board layout, there is a small stuf to go to a 7 seg display and I think it's some reflection. Probing another pin that doesn't go to the 7 seg doesn't show that hump and has a better looking rise time.
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